The present invention relates to the fabrication of integrated circuits. More particularly, the invention provides a technique, including a method and apparatus, for the deposition of a reduced-dielectric-constant, fluorine-doped insulating film in high-aspect-ratio trenches on semiconductor substrates.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition (CVD). Thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film.
The temperature needed for the surface reactions to occur can be reduced if a plasma is formed from the gases within the deposition chamber. Plasma promotes dissociation of the gases by the application of radio frequency (RF) energy to a reaction zone near the substrate surface, thereby creating a plasma of reactive species. The reactivity of the plasma species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such CVD processes.
The relatively low temperature of a plasma CVD process makes such a process ideal for the formation of insulating layers over deposited metal layers and for the formation of other insulating layers. In fact, while higher temperatures generally result in a higher deposition rate in thermal CVD processes, lower temperatures may result in higher deposition rates in plasma-assisted processes.
Semiconductor device density on chips has dramatically increased since such chips were first introduced several decades ago. One way to increase device density on a chip is to decrease the area per device. Typically, as device area decreases, the aspect ratios, i.e., the height relative to the width, of features on the device often increase. This is particularly true for metallization traces that maintain a cross-sectional area sufficient to carry the current required for device operation.
Additionally, as device area decreases, the spacing between device features gets smaller. Today's devices often have geometries with less than 1 .mu.m spacing between features. These effects combine to form closely spaced, high-aspect-ratio gaps that benefit from being filled with dielectric material.
Narrow, high-aspect-ratio gaps are difficult to fill in prior art CVD processes because the CVD material, accumulating on the corners of adjacent features as overhangs, often closes the gap from both sides before the gap is filled. FIG. 1A shows a vertical cross-sectional view of a partially processed substrate. The substrate has a conductive layer 115. This layer was previously deposited on substrate 100. Substrate 100 may be a wafer, specifically a semiconductor wafer, and more specifically, a silicon wafer. A first portion of a dielectric layer 130 has been deposited over the substrate. As shown, dielectric material has accumulated at the edges 135 to form overhangs 140.
FIG. 1B shows a vertical cross-sectional view of a substrate upon completion of the deposition of layer 150. Overhangs 140 have grown together, leaving an interior gap 145. This gap can cause problems relating to device fabrication, operation, and reliability. Various methods have been employed in an attempt to avoid forming this gap. One method is to deposit a partial layer of CVD dielectric, then to spin on a layer of low-melting-point glass that is subsequently heated so that it flows into and fills the gap. Other methods use sequential or concurrent deposition and sputtering to keep the gaps open until they are filled. Using a simultaneous deposition and etching process may also keep the gaps open until they are filled.
Because fluorine (F) is an etching species, fluorine simultaneously etches the layer as it is being deposited, and helps to keep the gaps open until they are filled. The simultaneous deposition and etching allows fluorine-doped silicon oxide films to have improved gap filling capabilities, such that the films are able to adequately fill gaps having an aspect ratio of between 1.8 to 4, or more, between adjacent metal layers. As is well known to those skilled in the art, fluorine-doped silicon oxide films are basically silicon dioxide modified with fluorine, and may vary in the local or the overall stoichiometric ratio of silicon to oxygen, and may be in an amorphous phase or a crystalline phase, or combinations thereof.
Another problem associated with higher device densities relates to the parasitic capacitive effects between conductive layers. Reducing the spacing between conductive layers often has the effect of bringing the plates of a capacitor closer together. This increases unwanted capacitance, resulting in several undesirable effects. For example, the resistive-capacitive (RC) time constant of a conductive trace may increase, requiring greater power for the same speed of operation of the circuit, or conductive layers may capacitively couple, resulting in "crosstalk." Lowering the dielectric constant of insulating layers between conductive layers would reduce these undesired effects by reducing the capacitance.
Many approaches to obtain lower dielectric constants have been proposed. One of the more promising solutions is the incorporation of fluorine or other halogen elements, such as chlorine or bromine, into a silicon oxide (S.sub.i O.sub.x) layer. Examples of halogen incorporation in films are described in U.S. patent application Ser. Nos. 08/548,391, filed Oct. 25, 1995 and entitled "METHOD AND APPARATUS FOR IMPROVING FILM STABILITY OF HALOGEN-DOPED SILICON OXIDE FILMS", 08/538,696, filed Oct. 2, 1995 and entitled "USE OF SIF.sub.4 TO DEPOSIT F-DOPED FILMS OF GREATER STABILITY", which are assigned to Applied Materials, Inc.
It is believed that fluorine, the preferred halogen dopant for silicon oxide films, lowers the dielectric constant of the silicon oxide film because fluorine is an electronegative atom that decreases the polarizability of the overall SiO-F network. Fluorinated silicon oxide films are also referred to as fluorinated silicon glass (FSG) films. Unfortunately, FSG layers may take a relatively long time to deposit.
FIG. 2 shows that increasing the relative concentration of silicon tetrafluoride silane (SiF.sub.4) to (SiH.sub.4) increases the time required to deposit a given thickness of dielectric, and that the rate of deposition decreases with increasing time or layer thickness. It is believed that this occurs because the plasma heats the surface of the layer as it grows. Fluorine acts as an etchant of the layer, and etching is more pronounced at higher temperatures and at higher fluorine concentrations.
Another factor affecting the deposition rate of the layer is that the layer may dissociate back into the plasma more rapidly at higher temperatures. This dissociation is in addition to any plasma etching and fluorine etching that may occur.
However, it is believed that more fluorine is incorporated into the growing layer at higher temperatures. Fluorine that is not incorporated, or is loosely incorporated, into the layer may remain as free fluorine. Free fluorine may absorb water, increasing the dielectric constant of the layer, and may form hydrofluoric acid, which can attack metal and oxide layers on the layer.
Incorporated fluorine reduces the dielectric constant of the layer, which is a desirable characteristic. However, the higher temperatures that increase fluorine incorporation also increase the etch rate and dissociation of the layer. Therefore, the desired temperature for greatest fluorine incorporation may result in an unattractively slow deposition rate.
FIG. 3 shows that the dielectric constant of a continuously deposited, fluorine-doped layer decreases with thickness. Therefore, a layer 401 deposited in a single step may have a graded dielectric constant, as shown in FIG. 4. Although the entire layer is shown as a sum of four sublayers, this is a representation. It is likely that the dielectric constant decreases in a monotonic fashion from an initial high value to a final low value. It is believed that this is due to the surface temperature of the layer increasing with time, which increases the fluorine concentration in the layer and reduces the dielectric constant.
Thus, manufacturers desire to include fluorine in various dielectric layers, and particularly in intermetal dielectric layers, to lower the dielectric constant. It is also desired that these layers be deposited in the least amount of time, and that the dielectric constant be fairly uniform across the layer. It is further desired that these layers fill gaps between features less than 0.5 .mu.m apart with an aspect ratio greater than 1.8.